The present invention relates to a semiconductor device and is applicable to a semiconductor device having a SRAM (Static Random Access Memory).
With reference to drawings, the basic structure of a SRAM cell that is a semiconductor memory element is described below.
As shown in a circuit diagram of FIG. 1, a SRAM cell is composed of a flip-flop circuit that functions as an information storage section and a pair of transmission transistors T1 and T2 that control the conduction between data lines (bit lines, BL1 and BL2) which serve for writing and reading of the information and the flip-flop circuit. The flip-flop circuit is made of, for example, a pair of CMOS (Complementary Metal Oxide Semiconductor) inverters, and each CMOS inverter contains a driver transistor D1 (D2) and a load transistor P1 (P2).
One side of source/drain regions in each transmission transistor T1 (T2) is connected to drains of a load transistor P1 (P2) as well as a driver transistor D1 (D2), and the other side thereof is connected to a bit line BL1 (BL2). Further, gates of a pair of the transmission transistors T1 and T2 each form a part of a word line WL and are connected with each other.
The gates of the driver transistor D1 and the load transistor P1 which constitute one of the CMOS inverters are connected to the drains (the storage node N2) of a driver transistor D2 and a load transistor P2 which constitute the other of the CMOS inverters. Further, the gates of the driver transistor D2 and the load transistor P2 which constitute the latter of the CMOS inverters are connected to the drains (the storage node N1) of the driver transistor D1 and the load transistor P1 which constitute the former of the CMOS inverters. In effect, a pair of CMOS inverters are arranged such that the input/output section of each CMOS inverters may be cross-coupled with the gate of the other CMOS inverter through one of a pair of interconnections L1 and L2, which are called the local interconnections.
Further, a reference voltage (Vss, for example, GND) is applied to the source region of each one of the driver transistors D1 and D2, and a supply voltage (Vcc) is applied to the source region of each one of the load transistors P1 and P2.
FIG. 2 is a diagram showing the ordinal layout of a conventional SRAM cell which corresponds to the circuit diagram of FIG. 1.
In the drawing, AR indicates an active region, in which a dopant diffusion region to constitute one of the transistors is formed. Further, an area shown by a chain line in the drawing is a region for one memory cell, and a number of memory cells are arranged side by side along the direction of the length of the word line to form an array, and arrays of memory cells are regularly disposed in the direction perpendicular to this direction of the length.
Referential numerals 117 and 118 indicate contact sections for the bit line BL1 and the bit line BL2, respectively; 121 and 122, contact sections for the supply voltage line; 123 and 124, contact sections for the reference voltage line (ground line). Contact sections 116, 111 and 113 are connected to one another through a local interconnection L1 which is not shown in the drawing, while contact sections 115, 112 and 114 are connected to one another through a local interconnection L2 which is neither shown in the drawing. The transmission transistor T1 is composed of a portion of the word line WL lying between the contact sections 113 and 117 and diffusion regions lying on both side thereof, and the transmission transistor T2, a portion of the word line WL lying between the contact sections 114 and 118 and diffusion regions lying on both sides thereof. The driver transistor D1 is composed of a portion of an interconnection 131 lying between the contact sections 113 and 123 and diffusion regions lying on both sides thereof, and the driver transistor D2, a portion of an interconnection 132 lying between the contact sections 114 and 124 and diffusion regions lying on both sides thereof. The load transistor P1 is composed of a portion of the interconnection 131 lying between the contact sections 111 and 121 and diffusion regions lying on both sides thereof, and the load transistor P2, a portion of the interconnection 132 lying between the contact sections 112 and 122 and diffusion regions lying on both sides thereof.
The SRAM cell described above has excellent element characteristics such as the high noise tolerance and the small stand-by power. Further, for the SRAM cell of this sort, in view of element characteristics, selection of the materials and layout are carefully made so as not to lose symmetry of the element structure (in other words, to prevent imbalance from occurring) within the limits of possibility,.
However, such a SRAM cell has a problem that a cell area tends to become considerably large, due to requirements to have 6 transistors in one memory cell and isolate p-type MOSFETs from n-type MOSFETs within one and the same cell as well as the need of numerous interconnections.
Accordingly, for a semiconductor memory device having a SRAM of this sort, an improvement in the integration level is one of the prime issues. Even if a reduction made in one memory cell is small, the degree of integration can be greatly raised, as a whole, in a semiconductor memory device of high integration. It is, therefore, important to make the area of the memory cell as small as possible. For that purpose, accompanying the recent progress in manufacturing technology, great efforts have been made to achieve, in addition to miniaturization of fabrication size and improvement of layout design, further reduction of the spacing of the interconnections as well as the distance between the interconnection and the contact section.
However, when the distance between the gate electrode of the transistor and the contact section disposed on the dopant diffusion region becomes excessively small, a problem of the leakage arises. This phenomenon occurs notably in the p-type MOSFETs which constitute the load transistors P1 and P2, and the standby current in the memory cell may increase, owing to the leakage generation. Such a phenomenon causes a serious problem, particularly in the Low Power type SRAM.
The generation of the leakage becomes marked, if the contact section for the source/drain region is in contact with the LDD (Lightly Doped Drain) region. One of the reasons for that is considered to be the movement of the dopants in the LDD region, being drawn to the side of the contact section. Since the dopant concentration in the LDD region is lower than that in the source/drain region which is a dopant diffusion layer of high concentration, the LDD region is readily affected by the dopants drawn thereto, with its dopant concentration being easily changed, and this may lead to a failure to form the junction as prescribed.
Further, the reason why the leakage is notable in the p-type MOSFETs is thought to lie in a fact that boron used as p-type dopants is liable to be drawn heavily to the contact section. Especially when a titanium-based metal film is employed as a barrier film to constitute the contact section, the leakage becomes marked. The explanation is considered to be made as follows. Due to the effects of a heat treatment conducted in fabrication, a titanium silicide layer is formed on a contact interface between the titanium-based metal film and the silicon substrate, and it is chiefly this titanium silicide layer that draws boron thereat.
Meanwhile, for the purpose of lowering the sheet resistance and the contact resistance caused by the contact section, a refractory metal silicide layer may be set over dopant diffusion regions which constitute source/drain regions. In Japanese Patent Application Laid-open No. 177067/1994, there is described a problem that, in such a structure, especially in a structure wherein a titanium silicide layer is formed over the dopant diffusion layer into which boron ions are implanted as dopants ions, some of the boron in the dopant diffusion layer may be drawn into the titanium silicide layer to form a low concentration layer therein. Against this, another dopant ion implantation is, in that publication, carried out to complement the very amount of a decrease in dopant concentration in the low concentration layer, and thereby non-ohmic characteristics are suppressed and the parasitic resistance is prevented from increasing.
However, for the LDD region where the dopant concentration is low and a shallow junction is formed, it is difficult to estimate, beforehand, the amount of the decrease in dopant concentration and complement that amount accurately by performing another ion implantation. Further, in forming such a LDD region, it is also difficult to set, accurately, the dopant concentration to be higher than the original one by the amount enough to compensate the subsequent decrease in concentration. Moreover, as described in the above publication, because the low concentration layer formed by the drawing movement of dopants is limited in the vicinity of the contact interface, the junction section may maintain a high dopant concentration and, as a result, a LDD region having a concentration profile of this sort may be produced. In this instance, original functions of the LDD structure are hard to be fulfilled so that deterioration of element characteristics may be brought about.
An object of the present invention is to develop technology capable to reduce the memory cell area while suppressing the generation of the leakage and to provide a semiconductor memory device of high integration with excellent element characteristics.
The present invention relates to a semiconductor device having:
a gate electrode which is formed on a first conductive-type well set in semiconductor substrate, with a gate insulating film lying therebetween;
a LDD structure in which, on either side of said gate electrode, there are formed a LDD region which is a second conductive-type dopant diffusion region with a low dopant concentration and a source/drain region which is a second conductive-type dopant diffusion region with a high dopant concentration;
an interlayer insulating film to cover said gate electrode as well as said section of LDD structure; and
contact sections which are formed by filling up openings made in said interlayer insulating film with a conductive metal; wherein:
a contact section connecting to one side of the source/drain regions having a potential equal to a potential of said first conductive-type well is disposed so as to come into contact with the LDD region lying on this side of the source/drain regions; and
a contact section connecting to the other side of the source/drain regions having a potential different from the potential of said first conductive-type well is disposed so as not to come into contact with the LDD region lying on this side of the source/drain regions.
Further, the present invention relates to a semiconductor device having a SRAM in which a memory cell comprises a pair of transmission transistors and a flip-flop circuit containing a pair of driver transistors and a pair of load transistors; wherein:
each one of said load transistors has:
a gate electrode formed on a semiconductor substrate, with a gate insulating film lying therebetween; and
a LDD structure in which, on either side of said gate electrode, there are formed a LDD region which is a dopant diffusion region with a low dopant concentration and a source/drain region which is a dopant diffusion region with a high dopant concentration; and, therein,
a contact section connecting to the source region is disposed so as to make a distance therefrom to the gate electrode in the direction of the gate length smaller than a width of the LDD region lying between the gate electrode and the source region in the direction of the gate length; and
a contact section connecting to the drain region is disposed so as not to come into contact with the LDD region lying on the side of the drain region.
Further, the present invention relates to a semiconductor device having a SRAM in which a memory cell comprises a pair of transmission transistors and a flip-flop circuit containing a pair of driver transistors and a pair of load transistors; wherein:
every one of said load transistors and said driver transistors has:
a gate electrode formed on a semiconductor substrate, with a gate insulating film lying therebetween; and
a LDD structure in which, on either side of said gate electrode, there are formed a LDD region which is a dopant diffusion region with a low dopant concentration and a source/drain region which is a dopant diffusion region with a high dopant concentration; and, therein,
a contact section connecting to the source region is disposed so as to make a distance therefrom to the gate electrode in the direction of the gate length smaller than a width of the LDD region lying between the gate electrode and the source region in the direction of the gate length; and
a contact section connecting to the drain region is disposed so as not to come into contact with the LDD region lying on the side of the drain region.
Further, the present invention relates to the semiconductor device as set forth above, wherein each one of said transmission transistors has:
a gate electrode formed on a semiconductor substrate, with a gate insulating film lying therebetween; and
a LDD structure in which, on either side of said gate electrode, there are formed a LDD region which is a dopant diffusion region with a low dopant concentration and a source/drain region which is a dopant diffusion region with a high dopant concentration; and, therein,
a contact section connecting to the source/drain region is disposed so as not to come into contact with the LDD region lying on the side of the source/drain region.
Further, the present invention relates to the semiconductor device as set forth above, wherein, at least, a bottom section of each contact section is composed of titanium or a titanium-containing material.
Further, the present invention relates to the semiconductor device as set forth above, wherein the dopant diffusion regions of said load transistors contain boron.
Further, the present invention relates to the semiconductor device as set forth above, wherein a refractory metal silicide layer is formed over a surface of every source/drain region in said load transistors, driver transistors and transmission transistors.
Further, the present invention relates to the semiconductor device as set forth above, wherein:
a contact section connecting to a drain region of a first load transistor which is one of said pair of load transistors and a contact section connecting to a drain region of a first driver transistor which has a gate electrode formed from a first conductive film interconnection A, the gate electrode being in common to said first load transistor, are formed, as one body, to constitute an inlaid interconnection set in a first insulating film which is an interlayer insulating film, and
said inlaid interconnection serves as one of a pair of local interconnections cross-coupling a pair of input/output terminals in said flip-flop circuit; and
a second conductive film interconnection formed from a second conductive film which is set on said first insulating film, with a second insulating film lying therebetween, constitutes the other one of said pair of local interconnections.
Further, the present invention relates to the semiconductor device as set forth above, wherein
said second conductive film interconnection is disposed so as to overlap at least a portion of a top surface of said inlaid interconnection, with said second insulating film lying therebetween; and
said inlaid interconnection and said second conductive film interconnection, separated by said second insulating film, constitute a capacitor element.
Further, the present invention relates to the semiconductor device as set forth above, wherein
said inlaid interconnection is disposed so as to make connection with
said drain region of the first driver transistor which is one of said pair of driver transistors;
said drain region of the first load transistor which is one of said pair of load transistors; and
a first conductive film interconnection B which constitutes a gate electrode of a second driver transistor which is the other one of the pair of driver transistors as well as a gate electrode of a second load transistor which is the other one of the pair of load transistors, and
said second conductive film interconnection is connected with
a contact section connecting to said first conductive film interconnection A which constitutes said gate electrode of the first driver transistor and the first load transistor;
a contact section connecting to a drain region of said second driver transistor; and
a contact section connecting to a drain region of said second load transistor.
The present invention can develop technology capable to reduce the memory cell area while suppressing the generation of the leakage, and provide a semiconductor memory device of high integration with excellent element characteristics having a low standby current.